Abstract
​In order to reduce circuit delay and help driving large fan-out, buffer insertion needs to be performed during logic and physical synthesis. This optimization activity is often done based on dynamic programming. We introduce a new and effective method in
which we combine Dynamic Programming and Branch and Bound techniques in order to improve the run time and quality of the buffer tree as compared to common methods. We solve the problem for the specific case of buffering balanced trees, where all loads have identical required time and input load capacitance. We provide the underlying concepts for a generalized version of our algorithm, where a set of different load capacitances and required times is given.

Keywords dynamic programming, runtime, delay, logic circuits, circuit synthesis, heuristic algorithms, NP-complete problem

Paper

BibTeX

@inproceedings{RabbaniMailhot:2007,
 author = {Rabbani, A. H. and Mailhot, F.},
 title = {Efficient Buffer Tree Creation Using Mixed Branch And Bound And Dynamic Programming Techniques},
 conference = {International Symposium on Signals, Systems and Electronics, ISSSE}, 
 year = {2007},
 doi = {10.1109/ISSSE.2007.4294496},
 publisher = {IEEE},
 location = {Montreal, Quebec, Canada},
}