Abstract As devices shrink, deep submicron designs demonstrate the increasing importance of interconnect delay on the circuit performance. In order to reduce interconnect delay and help driving large fanouts, buffer insertion needs to be performed during logic and physical synthesis. This optimization activity is often based on dynamic programming. In this dissertation, using the branch-and-bound technique, the problem for the specific case of buffering balanced trees is solved, where all loads have identical required time and input load capacitance. Necessary mathematical and data structural elements are provided to take into account a variety of design issues such as topology, buffer library and phase-shifting in the presence of inverting buffers. Combing dynamic programming and branch-and-bound techniques, a hybrid method is presented to improve runtime while memory consumption remains reasonably low. The underlying mathematical and algorithmic concepts given in this thesis can be used to generalize the proposed buffering method to produce a buffer tree for a set of different loads with different required time and capacitance.
@MastersThesis{Rabbani:Thesis:2007,
author = {Amir H. Rabbani},
title = {Circuit Delay Optimization By Buffering The Logic Gates},
school = {Department Of Electrical And Computer Engineering, Faculty Of Engineering,
Université de Sherbrooke},
year = 2007
}